Memory and bus architecture
RM0008
Table 1.
Register boundary addresses (continued)
Boundary address
0x4000 7800 - 0x4000 FFFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6800 - 0x4000 6BFF
Peripheral
Reserved
DAC
Power control PWR
Backup registers (BKP)
Reserved
bxCAN1
bxCAN2
Bus
Register map
0x4000 6000
(1)
- 0x4000 63FF Shared USB/CAN SRAM 512 bytes
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
USB device FS registers
I2C2
I2C1
UART5
UART4
USART3
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 3FFF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1800 - 0x4000 27FF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
USART2
Reserved
SPI3/I2S
SPI2/I2S
Reserved
Independent watchdog (IWDG)
Window watchdog (WWDG)
RTC
Reserved
TIM7 timer
TIM6 timer
TIM5 timer
TIM4 timer
TIM3 timer
TIM2 timer
APB1
1. This shared SRAM can be fully accessed only in low-, medium- and high-density devices, not in connectivity line devices.
2.3.1
42/995
Embedded SRAM
The STM32F10xxx features 64 Kbytes of static SRAM. It can be accessed as bytes, half-
words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.
Doc ID 13902 Rev 9
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